Low-Power High-Speed Circuit Design for VLSI Memory Systems

In modern computer systems, various memory components are used, such as on-chip register files, on-chip/off-chip cache memories, and off-chip main memories. High-speed memory system design has been and will have been one of the most important issues. In microprocessors, for example, the on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and the main memory. Power dissipation has also become an important consideration both due to the increased integration and operating speeds, as well as due to the explosive growth of battery operated appliances. In the thesis, low-power high-speed circuits for memories and processor-memory interface are investigated. First, abnormal leakage suppression (ALS) scheme is proposed to repair standby current errors in SRAMs due to device defects. By introducing leakage sensors, shift registers and fuses the ALS senses 1μA of abnormal leakage, isolates the memory cell systematically from VDD lines and thus suppresses abnormal leakage current. A 64Kbit test SRAM is fabricated in 0.6μm CMOS technology and the effectiveness are demonstrated. The area overhead decreases with the growth of memory capacity, and becomes less than 1% for 4Mbit SRAMs, which assures the practical use of this scheme in commercial applications. Next, research on active leakage power reduction for SRAMs are done by using two different approaches, dual supply voltage scheme, and row-by-row dynamic supply voltage scheme. In dual VDD design, cells are designed with high threshold transistors and operate at high VDD while peripheral logic circuits are designed with low threshold transistors and operate at low VDD. New pseudo NMOS type level converter with adaptive bias generator circuits is also proposed to bridge blocks operating at different voltage. Dual VDD scheme is implemented in a 2K-bit data/instruction cache SRAMs and a 256-bit register file inside a 16-bit microprocessor. Test chip is fabricated in 0.25μm fully-depleted SOI CMOS technology. The SRAM was measured and 400MHz operation at 0.5V/1.0V supply voltage is verified. The same scheme is also applied to a 256-bit register file, and measured. In the latter row-by-row dynamic supply voltage scheme, fine grain control mechanism is introduced, which uses an additional control signal line synchronized with a word line. Leakage current of un-accessed cells is reduced by lowering cell VDD together with a negative word line. The feature of the scheme is the utilization of DIBL effects which is one of the most prominent phenomenon in deep submicron transistors. It is pointed out that there are two different methods to implement RRDV scheme, PMOS switch type and NMOS switch type. They are compared and discussed taking various trade-offs into account. The effectiveness of RRDV scheme is verified with SPICE simulations and measurements and it is shown 99% leakage power saving is possible. In the latter part of the RRDV section, write power reduction with modified RRDV scheme is also investigated. Finally, a low-power yet high-speed chip-to-chip interface scheme, Wireless Superconnect (WSC) scheme is proposed with the density of 625 pins/mm. The interface utilizes capacitively coupled contact-less mini-pads, return-to-half-VDD signaling and sense amplifying F/F. The measured test chip in 0.35μm CMOS delivers up to 1.27 Gbps/pin with the power consumption of 3mW/pin. This high-density pad and low power feature is achieved mainly because of the elimination of ESD structure. Advantages over other conventional interfaces are also discussed in depth. The scalability of WSC scheme is investigated through SPICE simulations with 70nm predicted transistor model. It is shown that future 7000 I/O can operate at 8.0GHz with only 1.63W. The schemes proposed in this thesis can help build up a future low-power and high-speed memory system with reduced cost and turn-around time. Acknowledgments The research work described in this dissertation was carried out at the Institute of Industrial Science, the University of Tokyo, while I was a graduate student of the Department of Electric Engineering, the University of Tokyo form April 1998 to March 2003. As any graduate student would agree, a Ph. D. dissertation cannot possibly be accomplished without the immense encouragement and support of many others. I would like to thank my advisor, Prof. Takayasu Sakurai, the Institute of Industrial Science (IIS), the University of Tokyo, for providing valuable directions, freedom, and continuous encouragement for me. I am also grateful to Professors. Koichiro Hoh, Yoichi Okabe, Tadashi Shibata, Toshiro Hiramoto and Minoru Fujishima of the University of Tokyo for valuable comments at the examination of this dissertation. I would like to thank Professor Tadahiro Kuroda of Keio University for fruitful discussion about the Wireless Superconnect scheme. I would like to acknowledge Mr. Hiroshi Kawaguchi and Ken-ichi Inagaki for many technical discussions and supports throughout the work. I would also like to acknowledge all other members of Sakurai laboratory for giving valuable comments and encouragement. While I was engaged in Wireless Superconnect scheme, Mr. Hiroyuki Hara and Mr. Tetsuya Fujita at Toshiba Corporation gave me many valuable comments on ESD testing. They also kindly provided me many opportunities to use ESD tester at Toshiba. I would like to sincerely appreciate them. VLSI fabrications in this work were supported by VLSI Design and Education Center (VDEC), the University of Tokyo, Toshiba Corporation, NTT Corporation and NEC Corporation. The circuit simulator (HSPICE) has been supplied through VLSI Design and Education Center (VDEC), the University of Tokyo with the collaboration by Avant! Corporation. Finally, I would like to express my greatest appreciation to my parents, Motonori Kanda, Akiko Kanda, my sister, Hisako Kanda and my four grandparents, Hachio Kanda, Kazu Kanda, Nobuo Kasai, and Masuyo Kasai for their constant support and encouragement.